After pressing “run”, a sequence of hexadecimal values appear in the waveform view.
They appear to be counting properly as
shown in Figure 1; but another way of getting
a more complete view of this data quickly is
to turn on “chart mode”. A chart mode view
can be seen in Figure 2, but the expected
clean ramp is not seen.
Upon closer inspection, discontinuities are
seen at the transitions from hex value F to 0
in the least significant bit of the counter.
Validation with asynchronous capture
The next step of digging deeper is accomplished through timing validation with
asynchronous capture. This should sort out
whether there is a functional issue, a timing
issue or both.
In this mode, it is critical to sample and
view the clock signal, as well as the data
signal. An additional label is defined called
“clock” and the proper logic analyzer clock
input line is selected that has been physically
attached to the counter circuit clock signal.
The simplest trigger setup is just to enter the
value “FF” into the simple trigger menu next
to the counter bus in the waveform window.
00 (M2) and at the end of settled bus value
00 (M3). Simple timing measurements show
the amount of setup time (M1-M2) and hold
time (M3-M1) present, relative to the falling
edge of clock.
Often it is difficult to pinpoint a problem in
a design. Setting the right kind of trigger can
be crucial to getting to the bottom of a design
flaw. One of the most important trigger types
is called a timeout trigger. This makes the
logic analyzer watch for a repeating, expected
target system behavior and then trigger if that
behavior doesn’t happen within a certain,
expected time period. This is especially helpful when a target system has a data bus lock
up or hang to a fixed data value while the
clock continues to run.
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