Using Logic Analyzers to Reveal
Digital System Problems
Synchronous and asynchronous capture combined with the right triggering is the
key to efficient debug.
Today’s digital designs are evolving in a variety of ways, prompting new approaches to design, simulation, measurement and debug. One change
is the use of more serial buses. Another is the
use of system-on-a-chip (SOC) integrated
tal lines “asynchronously” from the system
under test. The measurement clock is gener-
ated by the logic analyzer rather than the
target system. Typically, that sampling hap-
pens faster than the target system clock rate,
ideally four times to even 10 times the system
Functional verification with
When a digital design physical prototype is
turned on, some designers first want to know
if the correct functionality is occurring in the
system through a variety of synchronous state-
circuits or advanced field-programmable gate arrays with SOC capability. Despite this evolution, there's
still a role for classic parallel buses in
many designs and the need to measure those buses.
Before looking at specific measurement examples, it is helpful to consider the difference between synchronous and asynchronous capture and
the benefits and limitations of each.
Synchronous (state-mode) capture
means that the measurement system
in the logic analyzer determines the
logic value of digital parallel buses or
control lines when there's an associated valid
clock, such as a rising edge on a system clock
line. The primary purpose of such measurements is to determine if the basic functionality of the system is correct.
In contrast, asynchronous (timing-mode)
capture means that the measurement system
samples the value of a bus or individual digi-
(Top Left) Figure 1: State (synchronous) capture
and trigger on “Counter = E7 hex”. (Bottom) Figure 2: Chart-mode view reveals discontinuities
in counter ramp. (Top Right) Figure 3: Close-up
timing view of “Clock” signal and “Counter” 8-bit
bus. Images: Agilent Technologies Inc.
clock rate. This allows one to see the “timing”
characteristics of the signals involved.
mode measurements. If something
doesn’t look right, they’ll then move to
asynchronous timing-mode measurements to see if they can figure out the
Let’s consider a simple 8-bit counter
circuit, and, for this particular example, the design was to produce counter
data that would be valid and settled
prior to the rising edge of a clock.
An initial evaluation of whether the
counter is working properly is made by
connecting eight data input lines of a
logic analyzer to the eight data bit output lines of the circuit.
The logic analyzer is placed in a state- or
synchronous-capture mode and clocking is
set up to capture data on the rising edge of the
clock signal. One easy place to set up a simple
trigger is from the waveform window. The
value hexadecimal E7 can be entered alongside
the bus name “counter” to define a simple trigger event (Figure 1).